Table of contents

Computer Organization

Computer Hardware Components

The five major components:

Memory, control unit, arithmetic unit, input devices, and output devices.

These fall into two broad groups. The logical structure is as follows:

• Main system

  • CPU—Central Processing Unit

    • Arithmetic unit: three registers and an arithmetic logic unit

      • ALU—Arithmetic Logic Unit

      • ACC—Accumulator

      • MQ—Multiplier-Quotient Register

      • X—Operand register

    • Control unit

      • CU—Control Unit: decodes instructions
      • IR—Instruction Register: holds the instruction currently executing
      • PC—Program Counter: identifies the next instruction. It increments automatically by 1 and has a direct path to MAR in the controller.

  • Memory—main memory (MM). It works through memory access: reading and writing according to memory-location addresses.

    • Memory array
      • Contains N memory locations
    • MAR—Memory Address Register: stores the address of the location to access. Its bit width determines the number of locations; a 10-bit MAR addresses 2^10^ = 1024 locations.
    • MDR—Memory Data Register: stores data read from memory or about to be written to memory. Its bit width equals the memory word length.

• Peripherals / I/O devices—Input/Output Equipment

  • Keyboard and mouse
  • Display

How a Computer Performs a Calculation

A computer instruction consists of an opcode + an address field.

The opcode specifies the operation (load, store, add/subtract/multiply/divide, halt, print, and so on).

The address field identifies where the operand is located in memory.

There are three stages:

1. Instruction fetch
2. Instruction decoding
3. Execution

For example, calculate $1 + 2$:

• The controller sends the address of the next instruction from PC to MAR, then to main memory over the address bus, and commands memory to read. Data from the location is sent onto the data bus and read into MDR. MDR transfers it to IR, which holds the current instruction. The instruction has now been read, completing the fetch stage.
• After the instruction reaches IR, IR sends its opcode to CU. CU decodes it as a load instruction.
• CU sends the instruction’s address field to MAR and commands memory to read. Operand 1 at that address is loaded into MDR and then transferred to ACC.
• After the first instruction completes, PC increments by 1 and the process repeats for the second instruction. CU decodes its opcode as addition and issues a memory read command. Operand 2 at the instruction’s address is read into MDR and then transferred to X. ALU performs the addition and places the result in ACC.

Calculating Storage Capacity

1. Total storage = main memory + secondary storage (the actual hard-drive capacity)

2. $\text{Main memory} = \text{Number of locations} \times \text{Word length} = 2^{\text{MAR bits}} \times \text{MDR bits} = 2^{\text{Address bus lines}} \times \text{Data bus lines (or bits)}$

   For example, with a 32-bit MDR and a 16-bit MAR, main-memory capacity is:

   $2^{16} \times 32 = 2^{21}$ bits

   Since 1 B (byte) = 8 bits and 1 KB = 1024 B, converting to KB gives:

   $2^{21} \div 2^{3} \div 2^{10} = 2^{8}$KB

   For example, with 10 address bus lines and 4 data bus lines, storage capacity is:

   $2^{10} \times 4 = 4K$