Table of contents

Computer Buses and Memory

A bus is a transmission path used by computer components to communicate and exchange information.

Multiple components can receive the same information from the bus simultaneously, but only one component may send information onto it at any given moment.

Bus Architectures

1. Dual bus
   • Memory bus, also called the M bus: connects the CPU and main memory.
   • I/O bus, or input/output bus: exchanges information between the CPU and I/O devices.
2. Single bus
   • There is just one system bus.
3. Three or more buses

System Bus

It consists of the following three parts:

Data Bus

The data bus exchanges data between components such as the CPU, main memory, and I/O devices. It is bidirectional. Number of data bus bits = data bus width

If the data bus is 8 bits wide but an instruction word is 16 bits, instruction fetch requires two main-memory accesses.

Address Bus

The address bus specifies the address of the memory location or I/O port that the CPU wants to access. It carries output from the CPU in one direction.

For example, to display the number 1 from a register on the screen, the CPU sends the address of the memory location containing 1 onto the address bus, and then also sends the address of the display onto it.

The number of address bus bits relates to the number of memory locations.

A 20-line address bus can address $2^{20}$ memory locations.

Control Bus

The control bus controls which component may use the bus at different times. It issues control signals to manage bus access. Transmission is unidirectional.

Bus Performance

Bus Width

This is the number of data bus lines, or bits, mentioned above.

Bus Bandwidth

The number of bits transmitted over the bus per unit time, usually measured as bytes transferred per second.

For example, with a bus frequency of 33 MHz and a width of 32 bits, the bandwidth is calculated below. 1 byte = 8 bits.

$33 \times (32 \div 8) = 132 MBps$

There are a few other factors, which I will not discuss in detail.

Memory

Main Memory

RAM-Random Access Memory

Random-access memory: any memory location can be accessed directly, and access time does not depend on its physical location.

ROM-Read Only Memory

Read-only memory: the data in its memory locations can be read but cannot be rewritten. After the initial information has been stored, during program execution it can only be read, not changed. ROM commonly stores fixed programs and constants.

Cache

Cache sits between the CPU and main memory. Because its capacity is very small, data must continually be loaded from main memory, replacing existing cache contents. Hardware handles this automatically.

Secondary Storage (Disks, Optical Discs, and Tape)

When the CPU needs data held in secondary storage, the operating system loads it into main memory for the CPU to use.

Main memory and secondary storage together form the operating system’s virtual memory system. If the logical address space used by the CPU is resident in main memory, it can be accessed directly. Otherwise, the operating system loads the corresponding physical contents into main memory before access.

Main-Memory Operations

In the logical computer architecture, main memory, MAR, and MDR are grouped under memory. In modern hardware, MAR and MDR are generally on the same chip as the CPU.

MDR and main memory exchange data over the bidirectional data bus.

MAR sends address information to main memory over the address bus.

Reading Data

The CPU’s CU sends the data address to MAR, which places it on the address bus for main memory. The CU issues a read command. Main memory reads the contents of that address and sends them over the data bus to MDR.

Writing Data

The CPU’s CU sends the destination address to MAR and then to the address bus. At the same time, it sends the data to MDR, which places it on the address bus. The CU then issues a write command. On receiving the command, main memory writes the information on the data bus into the memory location specified on the address bus.